European Patents (Registered in the United Kingdom, France, and Germany):
1,360,513 – MULTIPLE-CAPTURE DFT SYSTEM FOR DETECTING OR LOCATING CROSSING CLOCK-DOMAIN FAULT DURING SELF-TEST OR SCAN TEST

1,364,436 – METHOD AND APPARATUS FOR DIAGNOSING FAILURES IN AN INTEGRATED CIRCUIT USING DESIGN-FOR-DEBUG (DFD) TECHNIQUES 

1,370,880 – A MULTIPLE-CAPTURE DFT SYSTEM FOR SCAN-BASED INTEGRATED CIRCUITS

1,377,981 – A METHOD AND SYSTEM TO OPTIMIZE TEST COST AND DISABLE EFFECTS FOR SCAN AND BIST MEMORIES

Japan Patents:
4301813 – 自己試験中または走査試験中にクロックドメインにまたがる故障を検出するか突き止める複数キャプチャＤＦＴシステム MULTIPLE-CAPTURE DFT SYSTEM FOR DETECTING OR LOCATING CROSSING CLOCK-DOMAIN FAULT DURING SELF-TEST OR SCAN TEST

4733191 – 自己試験中または走査試験中にクロックドメインにまたがる故障を検出するか突き止める複数キャプチャＤＦＴシステム MULTIPLE-CAPTURE DFT SYSTEM FOR DETECTING OR LOCATING CROSSING CLOCK-DOMAIN FAULT DURING SELF-TEST OR SCAN TEST

4903365 – スキャンベースの集積回路でスキャンパターンをブロードキャストする方法および装置 METHOD AND DEVICE FOR BROADCASTING SCAN PATTERN BY SCAN-BASED INTEGRATED CIRCUIT

China Patent:
ZL02804862.1 – MULTIPLE-CAPTURE DFT SYSTEM FOR DETECTING OR LOCATING CROSSING CLOCK-DOMAIN FAULT DURING SELF-TEST OR SCAN TEST