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UltraScan™ is SynTest's solution to reduces test time 50x to 500x. It is used along with VirtualScan™ to reduce the overall test cost. UltraScan™ extends life of existing ATE for testing large SOC designs. It reduces test time and data volume for all scan designs with ATPG compression structures offered by VirtualScan™. With UltraScan™ a small number of high-speed I/O pads are adequate to run a scan ATPG test for a design with a large number of internal scan chains of shorter length. It achieves pin reduction through proprietary TDDM/ TDM circuitry. Overall shorter test load times are realizes by taking advantage of the unutilized bandwidth available on high-speed channels on the ATE during low-speed scan-shift operation. UltraScan™ also delivers better delay fault coverage for high-speed I/O pads on the device. Hardware overhead is predictable & low. VirtualScan™ and UltraScan™ provide a smooth migration into existing scan ATPG flow and also provide diagnosis support.
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Benefits
- Reduces test data volume of semiconductor testing – 5x to 50x
- Reduces test time – 50x to 500x
- Extends life of existing ATE for large SOC designs
- Reduces test time for all scan designs with ATPG compression structures
- A small number of high-speed I/O pads are adequate to run a scan ATPG test for a design with a large number of internal scan chains of shorter length
- Pin reduction realized through TDDM/TDM circuitry
- Overall shorter test load times by taking advantage of the unutilized bandwidth available on high-speed channels on the ATE during low-speed scan-shift operation
- High fault coverage
- Better delay fault coverage for highspeed I/O pads on the device
- Short test development time with no iterations
- Predictable & low hardware overhead
- Smooth migration into existing scan ATPG flow
- Diagnosis support
Features
- Patent pending, proprietary VirtualScan technology for broadcasting external scan chains (ATE channels) to many more – user defined - number of shorter internal scan chains and compacting them back into original number of external scan chains.
- Outputs complete virtual scan netlist
- Uses an enhanced virtual scan ATPG
- Static and dynamic compaction of ATPG patterns
- Advanced multiple clock domain handling using proprietary multiple-capture-per-cycle scheme
- Can be used with scan chains inserted using third party tools
- Fully compatible with SynTest’s existing DFT tools as well as TurboDiagnosis product line for debug, diagnosis, and failure analysis of scan chains
Platforms
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