Scan Synthesis and
ATPG - TurboScan™ 
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TurboScan™ is an advanced full-scan test suite. It includes a Scan Synthesizer (optional) and an Automatic Test Pattern Generator (ATPG). TurboScan automatically repairs testability violations to make your design highly testable. The ATPG engine uses advanced search and compaction algorithms to achieve very high fault coverage and produce a very compact test pattern set. TurboScan is designed to reduce product defect level and save test costs.
Scan Selection and Synthesis TurboScan supports flexible scan selection. It automatically performs scan selection based on your circuit's clock domains. The user can also specify a list of scan instances explicitly. The scan ports can be configured into single or multiple scan chains. TurboScan supports three scan cell types: Muxed scan, clocked scan, and LSSD. During scan synthesis, TurboScan automatically synthesizes circuitry to repair testability violations. TurboScan provides scan reordering capabilities to work with layout process to minimize the area overhead of scan chain routing. This also allows initial chip placement independent of scan stitching, further reducing the timing impact of scan insertion.
Scan Extraction and Debug TurboScan has built-in scan extraction utility to recognize any blocks in the design that contain pre-synthesized scan chains. It will then incorporate these existing scan chains into the rest of the design. In order to verify scan chain integrity and check for scan design rule violations, TurboScan automatically validates the scan chain architecture via simulation. This process is performed after scan synthesis is complete to ensure that valid test patterns can be shifted into and accurate results can be captured through the scan chains.
ATPG TurboScan includes ATPG engine to generate highly optimized test sets for full-scan designs. TurboScan ATPG algorithms work on designs containing gated clocks, RAMs, ROMs, tri-state gates, asynchronous set/reset, and unidirectional MOS transistors.
Very High Fault Coverage TurboScan contains advanced technologies to handle complex design structures for DFT which would otherwise result in low fault coverage. For example, TurboScan has special handling of bi-directional pins, transparent latches, bus contention resolution, rippled sets/resets, bus keepers, and multiple phase clocks. These types of structures usually cause many faults not detected by other ATPG tools. Instead of treating memories as black boxes, TurboScan can support write and read of memories. This allows faults surrounding the memories to be detected. TurboScan includes advanced ATPG search engine that uses a 32-value system (compared to the traditional 4-value system) to reduce the search space during ATPG. This improves the speed of the ATPG process and further increases the circuit's fault coverage.
Extremely Compacted Test Sets TurboScan produces very short test sets by utilizing both dynamic and static vector compaction. One major benefit of TurboScan is to provide a minimized number of tester cycles. This reduces the amount of tester memory needed and shortens the tester time required, and hence can significantly save you test costs.
Transition and Path-Delay Capability TurboScan also supports transition faults to detect difficult faults such as those at the tri-state enable pins. In addition, TurboScan's timing option generates test patterns for critical path delay faults and eliminates false paths from timing analysis.
Vector Conversion TurboScan converts ATPG test vectors into a variety of output formats, including both serial and parallel Verilog/VHDL testbench, WGL, and other vendor specific formats such as SONY and Chip Express.
Test Generation Modes
Supported Input Formats
Platforms
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