Fault Simulation -
TurboFault™ 
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High Performance Fault Simulation TurboFault™ combines high performance, versatility and accuracy. It is highly competitive with hardware accelerators for classical test fault grading. It supports synchronous and asynchronous designs at the gate level, including tri-state gates, latches, flip-flops, single and multi-port RAMs, complex bus resolution functions, and User Defined Primitives (UDPs). TurboFault reads Verilog gate-level netlists, and will also read Standard Delay Format (SDF) timing files.
TurboFault™ supports reporting of fault coverage for many fault models. Along with support for the traditional Stuck-At 1/0 fault model, support is also provided for fault models needed for deep sub-micron designs. Bridging Fault Support
TurboFault™ utilizes a new algorithm optimized for modern computer hardware that maximizes the power of today's workstations. SynTest Cached-Concurrent™ algorithm eliminates needless operations and with new Fast Queue™ technology combines the best of unit delay and cycle-based capabilities. No other fault simulator, hardware or software, matches the performance of TurboFault™. TurboFault™ makes fault simulation an integral design tool for generating a quality manufacturing test set. TurboFault™ supports single timing delay for simulation accuracy and flexibility, without sacrificing speed.
TurboFault™ is the fastest concurrent fault simulator based on the latest advances in cycle-based simulation technology. It simulates even faster than existing expensive hardware-accelerated fault simulators. Because fault simulation can consume memory very quickly, memory management is critical. TurboFault™ handles this by combining very efficient memory management, with special fault handling capability resulting in low memory consumption. TurboFault™
provides special handling for Oscillating and Hyper-active faults. Oscillating
faults are handled using a window approach. Any faults that oscillate
longer than the window time are considered oscillating and automatically
dropped. Hyper-active faults are also detected
Functional test vectors are not the only component of the fault simulation. Many customers use an ATPG tool to generate additional test vectors for the faults undetected by the functional test vectors. By utilizing its powerful system simulation capabilities, TurboFault™ integrates and fault grades test programs from many sources. TurboFault accepts Verilog VCD, WGL, TDL, and SynTest ATPG patterns as input stimuli.
TurboFault™ is intelligent enough to inspect the computer resources available and determine the optimal configuration for running a fault simulation job. If the number of faults is too large to fit into one computer at a time, TurboFault™ can partition the faults into separate groups and submit simulation tasks in multiple passes for each group. This automatic partitioning capability reduces the number of faults per pass and thus reduces paging. The results from different groups are then automatically merged in the final report. Incremental simulation reduces the number of vectors per run. A stimulus suite often consists of test pattern files where each pattern file requires a separate fault simulation session. Merging different fault grading reports is a tedious and time consuming effort. TurboFault™ provides an easy way to accumulate fault grading results from different fault simulation sessions. This frees the user to focus on analyzing the overall result instead of struggling with sorting individual reports.
TurboFault™ allows a user to define the criteria for a fault in order for it to be declared as detected. This gives the simulator the highest flexibility to emulate many test environments and Automated Test Equipment.
TurboFault™ can also be used as a simple diagnostic tool. The fault tracing feature allows users to compare the circuit activities between faulty and normal chips. This can speed up tuning test vectors, isolating faulty circuits and debugging failed parts.
TurboFault™ not only provides first rate performance but also power with second-to-none reliability. The crash recovery function allows recovery of the simulation data and protects results from any environmental adversities, such as network glitches and power outages. This feature ensures the highest and fastest rewards from the investment of time and computation resources.
TurboFault™ is one of the first EDA tools to adopt the powerful Tcl (Tool Command Language) user interface. Fault simulation control cannot be easier or more intuitive. Complicated fault simulation control can be quickly implemented in Tcl scripts with most common UNIX shells constructs available. The Tcl interface supports both batch and interactive modes. TurboFault™ accepts gate-level cell descriptions and User Defined Primitives (UDPs). SynTest also provides a cell library builder to build gate-level models. The library is compatible across all SynTest tools, including VirtualScan™ /TurboScan™ATPG. TurboFault™ supports Verilog gate-level and single timing models. TurboFault™ memory modeling provides basic memory building blocks for handling ROMs, and single and multi-port RAMs, either synchronous or asynchronous.
TurboFault™ produces concise, detailed reports on fault coverage and fault classifications. In addition, undetected faults can be passed directly to SynTest ATPG tools for additional processing. TurboFault™ reports faults as Hyperactive, Oscillatory, Hard Detect, Probably Detected, Potentially Detected, Undetected, or Uncompleted. Any or all of these can be combined in single or multiple reports which can be wrapped around as inputs for the next incremental fault simulation run, or passed to spreadsheet or plotting tools for analysis. Platforms
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