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RobustScan™ provides a platform for users to pick patented Configurable Soft-Error Resilience (CSER) cells or their preferred SER mitigation cells. First, Soft-Error Rate (SER) analysis is performed. Then it performs automatic robust-scan-cell and hardenedcombinational- cell selection and synthesis. Finally it generates verification testbenches for the final design. RobustScan™ can be used with scan chains inserted using third-party tools; it can be linked to third-party’s SER analysis programs and is fully compatible with SynTest’s existing DFT tools for test, debug, and diagnosis.
The RobustScanTM platform consists
of four major tools:
- Soft-Error Rate (SER) Analysis – allows users to identify and report the most susceptible logic blocks and run trade-offs to determine the best soft-error mitigation technique at the gate level.
- Robust-Scan-Cell and Hardened- Combinational-Cell Selection – allows automatically selecting or accepting a set of scan cells and combinational cells for soft-error protection, based on customer expectations on SER reduction.
- Robust-Scan-Cell and Hardened- Combinational-Cell Synthesis – allows automatically replacing the set of select cells with user-defined robust scan cells and hardened combinational cells and stitching them into an existing scan design.
- Testbench Generation and Verification – automatically generates Verilog testbenches to verify the correctness of the robust design.
Benefits
- Can reduce soft-error rate (SER) of a
system by 20X to 1,000X.
- Increases system reliability through
online soft-error protection.
- Performs SER analysis to identify logic
blocks (including combinational cells
and scan cells) that are most susceptible
to soft errors.
- Automatically replaces select scan cells
with robust scan cells that can detect or
correct the soft errors, given a SER
reduction requirement.
<<>Automatically replaces select combinational
cells with hardened combinational
cells that can reduce the SERs
of these select combinational cells and
overall SER of the chip.
- Supports existing circuit-level softerror
protection logic (referred to as
robust scan cells) currently practiced in
industry or proposed in academia.
- Accepts user-defined robust scan cells
and hardened combinational cells.
- Short test development time with no
iterations.
- Smooth integration with existing scan
synthesis and ATPG flow.
- Predictable & low hardware overhead.
- Debug/Diagnosis support.
* Works with commercially available logic and scan
synthesis tools from vendors like Cadence, Incentia, Magma, Mentor,
Synopsys or Synplicity.
Platforms
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