SynTest Unveils RobustScan Framework for Soft-Error Protection
"Tool Suite for Soft-Error Protection Using Robust Scan Cells"
SAN JOSE, Calif., July 23, 2009 -
SynTest Technologies, Inc., a leading supplier of Design-for-Test (DFT) tools, is unveiling a RobustScan framework to provide soft-error protection to scan-inserted designs.
Soft errors, also referred to as Single-Event Upsets (SEUs), are transient faults caused by various types of radiation. Radiation-induced transient faults can abruptly flip the stored state of a system and cause a system crash or even worse - a Silent Data Corruption (SDC) - if they are undetected. Atmospheric radiation such as cosmic rays, have long been regarded as the major source of soft errors. Reduced feature sizes, higher logic densities, shrinking node capacitances, lower supply voltage, and shorter pipeline depth have significantly increased the susceptibility of Integrated Circuits (ICs) to SEUs. Terrestrial radiation, such as alpha particles from the packaging materials of the chip, is also starting to cause soft errors with increasing frequency. This has also created system reliability concerns, especially for chips used in automotive, healthcare, and networking industries.
RobustScan provides a platform for users to pick patented Configurable Soft-Error Resilience (CSER) cells or their preferred SER mitigation cells. First, Soft-Error Rate (SER) analysis is performed. Then it performs automatic robust-scan-cell and hardened-combinational-cell selection and synthesis. Finally it generates verification testbenches for the final design. RobustScan can be used with scan chains inserted using third-party tools; it can be linked to third-party's SER analysis programs and is fully compatible with SynTest's existing DFT tools for test, debug, and diagnosis.
L.-T. Wang, founder, president & CEO of SynTest said, "One recent study conducted in 2005 on a design showed that almost half of the SER are from sequential elements, 40% SER are from memories, and the remaining from combinational logic. Studies also show that SER becomes more significant as process technology shrinks, indicating that SER is driven in part by a process. Thus, to cope with soft errors, one must incorporate effective protection mechanisms for combinational logic and scan cells, in addition to memories."
"Effective protection mechanisms are not just needed for technology nodes below 65 nm, users of enterprise servers and networking hardware demand limits on SER. SynTest customers in the automotive, aerospace, healthcare, and networking area will now benefit from the availability of the soft-error protection framework offered by RobustScan." added Ravi Apte, Vice President of Marketing at SynTest.
SynTest Technologies, Inc., established in 1990, develops IP for advanced Design-for-Test (DFT) and Design-for-Debug/Diagnosis (DFD) applications (including logic BIST, memory BIST, boundary-scan synthesis, Scan/ATPG with test compression, concurrent fault simulation, and silicon debug and diagnosis) and markets them throughout the world, to semiconductor companies, system houses and design service providers. SynTest products improve an electronic design's quality and reduce overall design and test costs. SynTest is headquartered in Sunnyvale, California, and has field offices in Taiwan, Japan, Korea and China, and distributors in Europe, Asia, and Israel. More information regarding SynTest is available at
SynTest Technologies Inc.
505 South Pastoria Ave., Suite 101
Sunnyvale, California 94086
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ATPG - Automatic Test Pattern Generation
BIST - Built-In Self-Test
CSER - Configurable Soft-Error Resilience
DFD - Design-for-Debug/Diagnosis
DFT - Design-for-Test
ECC - Error-Correcting Code
IC - Integrated Circuit
SDC - Silent Data Corruption
SER - Soft-Error Rate
SEU - Single-Event Upset
SynTest and VirtualScan
are trademarks of SynTest Technologies, Inc. All other trademarks are
property of their respective owners.
For more information:
SynTest contact info: Ravi Apte
Tel:1- 408-720-9956 ext. 300